Epitaxy is often used to merge individual fins that belong to a single transistor in order to provide enough material in the source drain for silicidation as well as to relax the requirements on a contact. Conventional epitaxy processes are not self-limited. This means that there is a variation in epitaxy thickness based on the fin-to-fin spacing to ensure that all fins that need to be merged are merged.
However, there is a need to avoid unwanted shorts between neighboring transistors as well as a source to drain shorts caused by the merging of fins of different transistors, and the variation in the epitaxy thickness makes it difficult to design growth rates to avoid the unwanted shorts. Known methods have employed extra spacing between neighboring transistors.
In conventional faceted epitaxy growth, the point where the tips of the facets merge is a weak point from a silicide formation point of view as there is not enough material in these to be consumed during epitaxy.
Accordingly, there is a need for an improved method for fin merge that prevents the unwanted shorts while providing for an adequate merge of fins in a transistor.